VHDL Program_blackjack

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity blackjack is port(card_out,green,red:out bit;
score:buffer std_logic_vector(7 downto 0);
data,d_data:in std_logic_vector(7 downto 0);
rst,newcard,finish: in bit; clk:in bit);
end blackjack;
architecture blackstruct of blackjack is
type state is (s0, s1, s2,s3, s4, s5, s6, s7);
signal p_state, n_state:state;
begin clock:
process(rst,clk)
begin
if rst='1' then p_state<=s0;
else if (clk'event and clk='1')then p_state<=n_state;
end if;
end if;
end process clock;
present: process(p_state)
--variable score_buf: std_logic_vector(7 downto 0);
begin
case p_state is when s0 => card_out<='0';
green<='0'; red<='0';
score<="00000000";
n_state<=s1;
when s1 => card_out<='0';
if newcard<='1' then n_state<=s2; else n_state<=s1;
end if;
when s2=> card_out<='1'; n_state<=s3;
when s3=> score<=score+data; n_state<=s4;
when s4=> if finish='1' then n_state<=s5;
else n_state<=s1;
end if;
when s5=> if score>d_data then green<='1';
else red<='1';
end if; n_state<=s0;
when others=> score <="11111111"; end case;
end process present;
end architecture blackstruct;